1. Field of the Invention
The present invention relates generally to data transmission, and more particularly to reducing jitter introduced by power supplies.
2. Description of Related Art
A SerDes, or Serializer/deserializer converts a parallel data stream to a serial data stream and vice versa. SerDes chips facilitate the transmission of parallel data between two points in high-speed serial streams over a differential media, reducing the number of signal paths and thus the number of connecting pins or wires required. SerDes devices may be used in wireless network routers, fiber optic communications systems, USB interfaces, PCIE (Peripheral Component Interconnect Express), and storage applications, and are capable of operating at speeds in excess of 10 Gbps.
Transmission jitter can include a random jitter component and a deterministic jitter component. Predicting causes of random jitter can be difficult. Deterministic jitter may result from conditions such as Duty Cycle Distortion (DCD), Data Dependent Jitter (DDJ), and Periodic Jitter.
DDJ, sometimes called Inter-symbol Interference (ISI), is usually the result of a bandwidth limitation problem in either a transmitter or physical media over which transmission is occurring. Reduction in transmitter or media bandwidth may result in varying amplitudes of data bits and changes in the time domain. Jitter depends not only on repeating-bit lengths, but also on states of preceding bits, so that jitter is correlated with the sequence of bits in a data stream.
FIG. 1 illustrates a currently available high-speed serial data transmitter which converts a parallel data input into a serial data output. As shown, an N to 2 multiplexer (MUX) 101 may convert N parallel input data streams into 2 parallel data streams: Dodd consisting of the odd numbered bits of a serial data stream D and Deven consisting of the even numbered bits of the serial data stream D. At the final stage of multiplexing the parallel data streams into the serial data stream D, a 2 to 1 MUX 102 may receive Dodd and Deven and combine them into the serial data stream D. A low jitter clock 103 may be used to retime the serial data stream D and to clean up the data, thus avoiding DDJ at the output of the 2 to 1 MUX 102. The low jitter clock 103 may be, e.g. a Phase Locked Loop (PLL). The clean data may then go to a pre-driver 104 before reaching a final transmitter driver 106. At this point, DDJ may start to accumulate due to limited bandwidth and non-ideal power supply.
Currently, inverter based pre-drivers are widely used in high-speed low power data communications. The pre-driver 104 may be coupled to a power supply 105, as shown in FIG. 1. The voltage output of the power supply 105 may fluctuate even when a dedicated regulated power supply is used. Not only is it difficult to keep the pre-driver power supply 105 constant over time, but also the fluctuation is often not able to settle before the next data bit arrives in high-speed data transmissions. The residue of a preceding data bit interferes with a next data bit or later bits through the power supply 105, introducing data dependent jitter (DDJ). The DDJ introduced by the power supply 105 is a primary jitter source in currently available high-speed low power transmitters.
One conventional way to reduce the DDJ introduced by the power supply 105 is to add decoupling capacitors to the power supply 105, in order to reduce the fluctuation in the power supply 105. However, adding decoupling capacitors to low impedance nodes may take a lot of space and is not efficient. Meanwhile, it may increase the settling time for the power supply 105 before the next bit arrives. The other extreme is to remove all decoupling capacitors on the power supply 105 to minimize the settling time, but in high speed applications, the power supply 105 still cannot settle within a bit time.
With careful design, data transitions may become fast enough so that the rise/fall of the current bit data does not depend on preceding bit states, and the major source of DDJ may be from the power supply. Therefore, it may be desirable to provide a method and apparatus which may reduce power supply introduced data dependent jitter in high-speed SerDes transmitters.